1. Field of the Invention
The present invention generally relates to a semiconductor package, and more particularly to a wafer level semiconductor package including substrate layer with higher packaging density of an integrated circuit.
2. Description of the Related Art
High efficiency, low cost, minimization and higher packaging density of a semiconductor package are objects that most electronic companies continuously attempt to achieve. The above-mentioned semiconductor packages are Multiple Chip Module/Stack/Ball Grid Array (MCM/Stack/BGA), Cavity Down Ball Grid Array (Cavity Down BGA), Flip Chip Ball Grid Array (Flip Chip BGA), Flip Chip Pin Grid Array (Flip Chip PGA) and Ball Grid Array which have active components and passive components.
However, the above-mention semiconductor packages generally include a substrate for supporting a semiconductor chip or for acting as an intermediate carrier between the semiconductor chip and a printed circuit board. Furthermore, the passive components are disposed in an extra space and on an extra area.
Referring FIG. 1, a conventional Chip Size Package (CSP) 2 includes a semiconductor chip 12 and a substrate layer 20 which is directly formed on an active surface 14 of the semiconductor chip 12. The substrate layer 20 includes two dielectric layers 15, 16 and a plurality of conductive traces 18. The dielectric layer 15 is disposed on the active surface 14 of the semiconductor chip 12. The conductive traces 18 are formed on the dielectric layer 15 and are electrically connected to a plurality of pads which are disposed on the active surface 14 of the semiconductor chip 12. The dielectric layer 16 is disposed on the dielectric layer 15 and the conductive traces 18, and parts of the conductive traces 18 are exposed out of the dielectric layer 16 so as to form a plurality of contacts. A plurality of solder balls 24 or conductive leads are disposed on the contacts for electrically connecting to an exterior device (not shown), e.g. a printed circuit board. A solder mask 26 is disposed on the dielectric layer 16 for surrounding the contacts 24. However, A much higher semiconductor package packaging density is still an object, in order to achieve minimization of the entire semiconductor package. In addition, the conventional Chip Size Package 2 cannot efficiently solve a problem that the passive components are disposed in an extra space and on an extra area. In other words, the semiconductor package must be provided with an extra space and on an extra area for receiving the passive components.
Accordingly, there exists a need for a semiconductor package capable of having a much higher integrated circuit packaging density.